Semiconductor memory devices include a plurality of columns formed by a first conducting line and a second complementary conducting line. Bit signals are stored in memory cells connected to one of the bit lines. Each memory cell usually includes a switch, which may be a transistor, and a capacitor for storing the bit signal. The switch selectively connects the memory cell to a bit line. The capacitor of each cell is at a high supply voltage or at a low voltage, according to whether the cell is storing a logic “1” or a logic “0”. Usually, in order to reduce the effects of a large mutual capacitance between adjacent bit lines, the complementary bit lines within a given column are twisted along the length of the column.
When reading the information stored in the memory cell, the capacitor is connected to the bit line of the column. Since the bit lines are normally quite long, its capacitance is much larger than the capacitance of the cell capacitor. Therefore, the potential of the bit line will only slightly be modified by the charge of the capacitor. In order to traduce this small voltage signal in a full logic signal, semiconductor memory devices are provided with sense amplifiers.
Sense amplifiers can be implemented in memory devices according to several designs. A memory circuit 700 according to a first known design is shown in FIG. 10. The sense amplifier 710 includes a pair of cross-coupled inverters 711, 712 connected to the bit lines 701 and 702 and is switched on/off by a transistor 750 driven by a reference voltage. Before starting a read/write procedure, the bit lines are at pre-charged at ground. However, the sense amplifier 710 is only stable when one of the two bit lines is “low” and the other is “high”. Because of the pre-charging to ground, a reference cell 770 is needed in order to place a reference voltage on the bit line complementary to the bit line connected to the memory cell.
The reference cell 770 comprises two access transistors 772 and 773 and a capacitor 771. The reference cell 770 is provided at the intersection of a dummy word line WLref and the connecting line 702. The transistor 773 is turned on by activation of the dummy word line WLref, whereby the dummy capacitor 771 is electrically connected with the bit line 702. The transistor 772 is turned on by activating the signal line Pref when the dummy word line WLref is inactive, thereby electrically connecting the dummy capacitor 771 and a voltage line Vref to each other. The voltage line Vref supplies the power supply voltage Vdd/2.
During a refresh operation of the bit “0”, no charge appears on the bit line 701 (equation 1.1), while the bit line 702 (complementary bit line BLC) will have a voltage given by:VBLT=0  (1.1),VBLC=Cmem·0.5·Vdd/(Cmem+CBL)  (1.2)
wherein Cmem is the capacitance of the memory capacitor 762 and CBL is the capacitance of the bit line. On the other hand, during a refresh operation of the bit “1”, the signal on the bit line 701 (true bit line BLT) is given by the equation (2.1), while the signal of on the bit line 702 is given by equation (2.2) below:VBLT=Cmem·Vdd/(Cmem+CBL)  (2.1)VBLC=Cmem·0.5·Vdd/(Cmem+CBL)  (2.2).
Subsequently, the difference of the potential value on the bit lines 701 and 702 is sensed by the sense amplifier. At the end of the cycle, the signal Pref is fed into the gate of the transistor 772 of the reference cell 770 so as to connect Vref to the dummy capacitor 771 and pre-charge the dummy cell to Vdd/2.
The use of bit line twisting complicates the reference cell scheme. Indeed, for each region defined by a bit line twisting is needed a memory cell. Moreover, in common memory circuits half of the memory cells are connected to the first bit line 701 and half to the second bit line 702 in order to reduce the load. Therefore, the sense circuit illustrated in FIG. 10 requires a high number of reference cells and dummy word lines in order to properly function. As an example, considering a memory column with 128 rows and one twisting point at row WL63, four dummy word lines are required.
In conclusion, the structure of FIG. 10 needs a high number of dummy cells, thereby increasing the overall dimensions of the memory array. Moreover, the memory device has to de designed so as to support high voltage for driving any of the dummy rows in the reference cells. Finally, any reference cell needs a power supply for supplying Vref to the reference cell.
FIG. 11 illustrates another known scheme for a memory circuit 800 including a sense amplifier 810. The sense amplifier 810 includes a pair of cross-coupled inverters 811, 812 between the bit lines 801 and 802 and is switched on/off by a transistor 850 driven by a reference voltage. In the memory circuit 800, the bit lines 801 and 802 are pre-charged at Vdd/2.
During a refresh operation of the bit “0”, the storing capacitor 861 is at zero potential and when it is connected to the bit line 801, the bit line 801 is slightly discharged and its potential is decreased by δV. After this equalization procedure, the bit line 801 will be at the potential Vdd/2−δV. On the contrary, the bit line 802 remains at Vdd/2. The difference in the potentials of the bit lines 801 and 802 is sensed by the sense amplifier 810 as a logical “0”.
During a refresh operation of the bit “1”, the storing capacitor 861 is at Vdd. When the storing capacitor 861 is connected to the bit line 801, it discharges into the bit line 801, thereby increasing the potential of the bit line 801 by δV. After equalization the bit line 801 is at a potential Vdd/2+δV, while the bit line 802 remains at Vdd/2. The difference in the potentials of the bit lines 801 and 802 is sensed by the sense amplifier 810 as a logical “1”.
Although the structure of the memory circuit 800 of FIG. 11 is rather simple, an extra supply is needed in order to pre-charge the bit lines at Vdd/2. This causes an increase of the power consumption of the memory device. Moreover, pre-charging the bit lines at Vdd/2 also reduces the operating speed of the memory device.
A further known schema for a sense circuit is shown in FIG. 12. The memory circuit 900 has the bit lines 901 and 902 pre-charged at ground. In order to be able of correctly sense a “0” bit, while eliminating the reference cells used in the memory circuit 700 of FIG. 10, the sense amplifier 910 is “unbalanced”. More precisely, the transistors constituting the sense amplifier are different so as to generate an “unbalanced” flow of current through the sense circuit 910. Accordingly, reading of a “1” bit can be differentiated from reading of a “0” bit.
The memory circuit 900 has a simple structure and does not need to pre-charge the bit lines 901 and 902 at a predefined potential. However, in order to correctly read a “0” bit, the sense amplifier has to be unbalanced. This unbalance causes an uncontrolled variation of the switching point depending on variations of the Process-Voltage-Temperature parameters (functional PVT).
The switching point is a crucial parameter that may drastically affect the performance of the sense amplifier and represents the value of bit signal on a bit line for which the amplification time is maximum. More precisely the switching point represents a “threshold” voltage that divides the range of voltages at which a data signal is read as a logic “1” from the range of voltages at which a data signal is read as a logic “0”.
Moreover, at low temperatures and voltages, threshold voltage temperature inversion only occurs in the cross-coupled PMOS transistors of the sense amplifier 910, but not in the remaining components of the sense amplifier 910. Consequently, in this scheme, the standard deviation of the switching point is very high at low temperatures and voltages. Therefore, the above described sense amplifier is not suited for low voltage operations.
Summarizing, sense amplifiers common used in semiconductor memory devices either have a very complex structure which produces reliable results but cause the memory device to be bulky and increase the power consumption of the memory device, or have a simple structure but are very sensitive to variations in the PVT parameters, have a very high standard deviation of the switching point and cause an uncontrolled variation of the switching point.